1. Field of Invention
This invention relates to a semiconductor device, and a method for fabricating a semiconductor device.
2. Description of Related Art
Trapping-type memory devices, which include a charge-trapping layer instead of a floating gate between the substrate and the control gate, have been widely applied in the related fields.
In a conventional fabrication process of the trapping-type memory, the control gates are defined after the corresponding conductive layer is deposited over the charge-trapping layer, source/drain (S/D) regions are formed in the substrate after a spacer is formed on the sidewall of each control gate, and the trapping layer is not patterned between the step of defining the control gates and the step of forming the spacer.
Because the charge-trapping layer is not patterned before the spacer defining the bounds of the S/D regions is formed, metal silicide cannot be formed on the S/D regions. Hence, the sheet resistance of the S/D regions is high so that the device speed is lowered. Furthermore, the contact resistance of the S/D regions is high even open.